1. Field of the Invention
The present invention relates to an insulated gate bipolar transistor (IGBT) and a method of fabricating the same, and a semiconductor device including an IGBT and a method of fabricating the same.
2. Description of the Background Art
FIG. 17 is a sectional view showing the sectional structure of a conventional lateral IGBT. This IGBT is fabricated as follows: First, an impurity is diffused in a part of an n-type base layer 1 having a relatively low impurity concentration, to form an n-type buffer layer 2 having a relatively high impurity concentration. Then, a gate insulating film 24 and a polysilicon film 3 serving as a gate are selectively formed on the n-type base layer 1. Then, the polysilicon film 3 is employed as a mask for depositing and thereafter diffusing an impurity from the left side in the figure into an upper layer part of the n-type base layer 1, for forming a p-type base layer 4. At the same time, a p-type collector layer 19 for serving as collector is selectively formed on a surface of the n-type buffer layer 2 by diffusion. Then, an n-type emitter layer 17 for serving as an emitter is formed on a surface of the p-type base layer 4.
FIG. 19 is a plan view showing the plane structure of the conventional transversal IGBT. A section taken along the line A--A in FIG. 19 corresponds to FIG. 17. As shown in FIG. 19, the p-type base layer 4, the n-type emitter layer 17, the gate electrode 3, the n-type base layer 1, the n-type buffer layer 2 and the p-type collector layer 19 have elliptic plane shapes respectively, so that the n-type emitter layer 17 is formed inside the p-type base layer 4, and the gate electrode 3, the n-type base layer 1, the n-type buffer layer 2 and the p-type collector layer 19 are successively formed inside the n-type emitter layer 17 in a similar manner to the above.
Finally, an emitter electrode 20, a gate electrode 21 and a collector electrode 22 are formed on parts of the p-type base layer 4 and the n-type emitter layer 17, the polysilicon film 3, and the p-type collector layer 19 respectively. Thus, the lateral IGBT is formed as shown in FIG. 17. In sectional views which are hereinafter referred to, one-dot chain lines may be drawn along centers of p-type collector layers 19, to indicate that the p-type collector layers 19 are planarly positioned at the centers.
According to the conventional IGBT structure, the gate electrode 21 and the emitter electrode 20 are grounded, and the n-type buffer layer 2 suppresses spreading of a depletion layer when a positive voltage is applied to the p-type collector layer 19. When a voltage which is positive with respect to the emitter electrode 20 is applied to the gate electrode 21, an n-type channel is formed on a surface of the p-type base layer 4 under the gate 3, and electrons flow into the p-type collector layer 19 through the n-type base layer 1. At this time, holes are injected from the p-type collector layer 19, in order to satisfy a charge neutrality condition. Thus, conductivity modulation is increased and an ON-state voltage is reduced as compared with a power MOSFET.
Switching loss is generally expressed by the product of an ON-state voltage and a turn-off time. In order to reduce power consumption, therefore, desired is an IGBT having a low ON-state voltage and a short turn-off time for reducing switching loss.
An IGBT which is expected as a high withstand voltage element has an important object of improvement in withstand voltage as a matter of course, and IGBTs which are aimed at improving withstand voltages have been announced in various structures, while these IGBTs have such disadvantages that absolutely no consideration is made on ON-state voltages.
In a power IC, it is necessary to form a low withstand voltage element such as a CMOS element for forming a logic circuit on the same substrate as a high withstand voltage element such as an IGBT. FIG. 18 is a sectional view showing the sectional structure of an n-channel MOSFET. First, a p-type well diffusion layer 7 is formed in the same n-type base layer 1 as a high withstand voltage element. A gate insulating film 23 and a polysilicon film 8 serving as a gate are selectively formed on a surface of the p-type well diffusion layer 7. Then, the polysilicon film 8 is employed as a mask to form n-type diffusion layers 9 and 10 of relatively high concentrations for serving as source and drains on both sides of the polysilicon film 8 on the surface of the p-type well diffusion layer 7. Then, a drain electrode 64, a source electrode, and a gate 66 are formed on the n-type diffusion layer 9, the n-type diffusion layer 10, and the polysilicon film 8 respectively. Thus, a low withstand voltage MOSFET shown in FIG. 18 is formed.
In the aforementioned fabrication steps of the high withstand voltage element (IGBT) and the low withstand voltage element (MOSFET), both the p-type base layer 4 of the high withstand voltage element and the p-type well diffusion layer 7 of the low withstand voltage element are diffusion layers for forming channel parts. However, these must be formed through separate steps, for the following reason:
The p-type base layer 4 for serving as a p-type channel part of the high withstand voltage element is formed by diffusing an impurity after deposition from the left side of a position A through the polysilicon film 3 serving as a mask, and hence the p-type channel part provided under the polysilicon film 3 is formed by transversal diffusion. Namely, there is such a tendency that the impurity concentration is rightwardly reduced from the position A.
On the other hand, the p-type well diffusion layer 7 for serving as a p-type channel part of the low withstand voltage element is formed before formation of the polysilicon film 8, and hence the same is formed by longitudinal diffusion from the surface of the n-type base layer 1, whereby a uniform impurity concentration can be attained in the transversal direction.
Thus, there is an essential difference between the methods of forming the channel parts in the high withstand voltage element and the low withstand voltage element, and hence the implanation doses of the impurities are different from each other in the p-type base layer 4 and the p-type well diffusion layer 7. Further, the p-type channel part of the high withstand voltage element utilizes transversal diffusion of the p-type base layer 4 as described above, whereby a channel length L is inevitably decided by the depth of the diffusion. Thus, it is necessary to design the depth of the diffusion in the high withstand voltage element independently of the low withstand voltage element.
Thus, the fabrication steps for the conventional IGBT which is employed for a power IC are independent of those for the field effect transistor which is a simultaneously integrated low withstand voltage element, and the fabrication steps are inevitably complicated in order to integrate both on one chip.